An embodiment relates to a method of programming a nonvolatile memory device.
There is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and can retain its data even without the supply of power. In order to develop high-capacity memory devices capable of storing large data, high integration technologies for memory cells are being developed. A nonvolatile memory device includes a memory cell array consisting of a plurality of strings. A single string includes a plurality of memory cells coupled in series.
The memory cell includes a gate in which a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate are stacked over a semiconductor substrate and junction regions formed in the semiconductor substrate on both sides of the gate. During the program operation, hot electrons are injected into the floating gate. During the erase operation, electrons injected into the floating gate are discharged by F-N tunneling.
FIG. 1 is a sectional view showing the unit cell string of a nonvolatile memory device.
The unit cell string of the nonvolatile memory device includes memory cells respectively coupled to first to thirty-second word lines WL0 to WL31 between a drain select line DSL and a source select line SSL.
In the nonvolatile memory device comprising a number of the unit cell strings, when a program operation is performed, a program voltage (Vpgm) is applied to a selected word line, and a pass voltage (Vpass) is applied to the remaining word lines. Furthermore, a power supply voltage is supplied to the drain select line DSL, and 0 V is applied to the source select line SSL.
Accordingly, a transistor coupled to the drain select line DSL is turned on, and a transistor coupled to the source select line SSL is turned off. However, as voltage of a channel boosting area rises due to the occurrence of channel boosting, the transistor coupled to the drain select line DSL is also turned off.
FIG. 1 is a diagram showing voltages applied in the case where the thirtieth word line WL29 is selected for a program. A program voltage (Vpgm) is applied to the thirtieth word line WL29, and a pass voltage (Vpass) is applied to the remaining word lines.
The program voltage (Vpgm) is applied to not only the selected memory cell, but memory cells coupled to other cell strings arranged on the same word line. Consequently, unselected memory cells coupled to the same word line can be programmed. Such a phenomenon is called a program disturbance phenomenon.
To prevent the program disturbance phenomenon, a bit line to which the unselected memory cells are coupled is charged to a level (Vcc-Vth) (where Vcc is the power supply voltage and Vth is the threshold voltage of the drain select transistor) so that the channel voltage (Vch) of each cell string is boosted during the program operation, thereby preventing the unselected memory cells from being programmed.
In this case, if the channel boosting level is low, program disturbance resulting from F-N tunneling can be generated. If the channel boosting level is high, program disturbance resulting from injection of hot electrons can be generated. Accordingly, the pass voltage (Vpass) applied to the word lines may be controlled for adequate channel boosting.
Furthermore, channel boosting may be hindered by the threshold voltage levels of memory cells neighboring a selected memory cell. To solve this problem, an erase area self-boosting method may be used.
FIG. 2 is a sectional view of a cell string for illustrating the erase area self-boosting method. In FIG. 2, the cell string is coupled to an unselected bit line.
Referring to FIG. 2, in the erase area self-boosting method, a program voltage (Vpgm) is applied to a thirtieth word line WL29 selected for a program, 0 V is applied to a twenty-ninth word line WL28, and a pass voltage (Vpass) is applied to the remaining word lines. For example, a power supply voltage VCC is applied to the unselected bit line.
Furthermore, the power supply voltage is applied to a drain select line DSL, and 0 V is applied to a source select line SSL.
Accordingly, a transistor coupled to the drain select line DSL is turned on, and a transistor coupled to the source select line SSL is turned off. However, channel boosting is generated, and so the transistor coupled to the drain select line DSL is also turned off because of high channel boosting.
If word line voltages are applied as described above, high channel boosting is generated from the twenty-ninth word line WL28 toward the drain select line DSL, and so a transistor coupled to the twenty-ninth word line WL<28> is not programmed. Low channel boosting is generated from the source select line SSL to the twenty-ninth word line WL28.
The erase area self-boosting method is very efficient in the case where memory cells placed from a selected memory cell toward the drain select line are not programmed, but raises a concern in that the number of memory cells participating in boosting is limited in the case where there are programmed memory cells among memory cells and the programmed memory cells are placed from a selected memory cell toward the drain select line.
With the size of a nonvolatile memory device gradually decreasing, the length and width of the gate of a cell also decreases. Accordingly, if a small number of limited cells take part in channel boosting, the capacitance value of a channel becomes very small, which is not sufficient for reducing effects from the leakage current. Accordingly, a program is influenced here because a channel potential is reduced even by a low leakage current.
Furthermore, if the number of cells participating in boosting is reduced, an influence by a high program voltage is increased, resulting in a high boosting channel potential. Accordingly, the number of electrons generated by a gate induced drain leakage (GIDL) phenomenon is increased. Further, a disturbance fail can occur because of hot electrons generated by a strong electric field caused by a difference in the high potential.